This invention relates generally to automatic test equipment, and more specifically to the use of programmable digital devices for monitoring and controlling parametric measurement units in automatic test equipment.
Automatic test equipment (also known as a xe2x80x9ctesterxe2x80x9d) is widely used to test semiconductor devices, printed circuit boards, and other electronic components and assemblies. Many testers, especially those that are used to test semiconductor devices, use xe2x80x9cpin slicexe2x80x9d architecture. Such testers generally include multiple pin slice circuits, each associated with a separate pin on a device under test (DUT). Further, each pin slice circuit generally includes circuitry for generating and measuring signals at its associated pin on the DUT.
A typical tester may generate and measure signals on hundreds to a few thousand pins, each pin having its own pin slice circuitry. This means that pin slice circuitry is duplicated hundreds or thousands of times in a tester. It is therefore very important for testers to use pin slice circuits that are both area and cost efficient.
In addition, during a typical test session, it is often necessary to vary one or several analog reference voltage levels used in each pin slice circuit. This is especially the case when performing parametric tests of a DUT""s drive and receive levels.
For example, a sequence of reference voltage levels may be generated and provided to certain sections of the pin slice circuits. If the steps of generating and providing changes in the reference voltage levels require a large amount of time, then the time to complete the full test session could become very long, especially if the test session calls for the generation of sequences of hundreds of different reference voltage levels. It is therefore very important for testers to communicate the desired reference voltage level changes and generate new reference voltage levels quickly.
However, pin slice circuits must also generate and measure signals with a high degree of accuracy. This is because any inaccuracy in signal levels generated or measured by pin slice circuits will generally affect the accuracy of test results. In particular, it is very important for pin slice circuits to generate stable voltage and current levels during parametric tests. Further, pin slice circuits must generate and measure signals at levels that are compatible with the semiconductor devices being tested.
One way of satisfying these competing requirements is to design pin slice circuits using a combination of different component technologies. For example, pin slice circuits have been designed using a combination of CMOS and bipolar component technologies.
Primarily because of the low power requirements of CMOS components, CMOS has become the technology of choice for many designers of computers and electronic devices. Consequently, CMOS components have become widely available and relatively inexpensive. Further, because of the desire to make computers and electronic devices both faster and smaller, the dimensions of CMOS components have decreased significantly over the years. Accordingly, portions of pin slice circuits have been designed using CMOS technology in an effort to make the circuits lower cost and more compact.
However, one shortcoming of designing circuits using CMOS technology is that it can lead to unstable and unpredictable timing characteristics. For example, timing characteristics of identical CMOS circuits have been found to vary from component-to-component.
Further, timing characteristics of CMOS components have been found to vary with temperature. For example, as frequencies of signals processed by CMOS components increase, power requirements of the CMOS components also generally increase, thereby causing the components to heat-up. This increase in temperature can affect propagation delays through the CMOS components.
Generally, this shortcoming of CMOS technology does not seriously affect the performance of most computers and electronic devices because CMOS circuits in these devices are usually synchronized with an internal clock. Such synchronous design techniques are often used to enhance the stability and predictability of electronic circuits.
Although some portions of pin slice circuits can also be synchronized with a clock inside the tester, the timing of other portions of pin slice circuits cannot be similarly synchronized. For example, the times at which pin slice circuits generate and measure signals at pins of a DUT are usually determined by the DUT, not by a clock internal to the tester.
Accordingly, when CMOS technology is used to implement circuitry for generating timing signals in pin slice circuits, compensation techniques must generally be used to improve the timing characteristics of the CMOS circuitry. Such compensation techniques are described in U.S. patent application Ser. No. 08/510,079, assigned to TERADYNE(copyright), Inc., Boston, Mass., USA.
Another reason why CMOS technology is sometimes not used to implement the signal generation portions of pin slice circuits is that CMOS circuits generally have low drive capabilities.
For these reasons, bipolar technology is often used for implementing signal generation and measurement portions of pin slice circuits in conventional testers. Timing characteristics of circuits made with bipolar technology are generally more stable and more predictable than CMOS circuits. Further, bipolar circuits can generally drive and measure signals at higher power levels than CMOS circuits.
Such a conventional tester 100 is shown in FIG. 1. The tester 100 includes a test system controller 110, which includes a special purpose computer (not shown); and, a memory 124, which stores test results and information needed to control the tester 100. Both the test system controller 110 and the memory 124 are normally implemented using CMOS technology. This is because the test system controller 110 and the memory 124 are typically synchronized with a test system clock. Further, neither the test system controller 110 nor the memory 124 is required to drive or receive signals with high power levels.
The tester 100 also includes multiple pin slice circuits 114, which generate and measure signals at separate pins of a DUT 112, which might be a discrete semiconductor device or one of a plurality of dies on a semiconductor wafer.
Each pin slice circuit 114 typically has portions that are implemented using either CMOS or bipolar technology. For example, the pin slice circuits 114 include timing generators 116, which may be implemented using CMOS technology. In this case, the compensation techniques mentioned above are typically used to improve timing characteristics of the CMOS circuits. The timing generators 116 produce timing signals in response to commands from the test system controller 110 for determining times at which driver/receiver channels 118 drive or measure digital signals at pins of the DUT 112.
The driver/receiver channels 118 in the pin slice circuits 114 are typically implemented using bipolar technology. This ensures that the driver/receiver channels 118 have the capability of driving and measuring digital signals at pins of the DUT 112 at the proper times.
Two of the pieces of information that the test system controller 110 uses to control the pin slice circuits 114 indicate values of logical high and logical low levels to be provided by the driver/receiver channels 118 to the DUT 112; and, values of logical high and logical low levels to be received by the driver/receiver channels 118 from a properly functioning DUT 112.
In particular, the pin slice circuits 114 include reference voltages 122, which are typically implemented using discrete analog circuitry. The reference voltages 122 provide multiple reference voltages to the driver/receiver channels 118. Accordingly, the test system controller 110 provides information to the driver/receiver channels 118 indicating which reference voltages to use as logical high levels and logical low levels.
The pin slice circuits 114 also include parametric measurement units (PMU""s) 120, which are typically implemented using bipolar technology and discrete analog circuitry. Whereas the driver/receiver channels 118 generate and measure digital signals, the PMU""s 120 produce and measure DC levels.
The reference voltages 122 also provide multiple reference voltages to the PMU""s 120. The test system controller 110 therefore provides information to the PMU""s 120 indicating which reference voltages to use when producing and measuring DC levels at pins of the DUT 112.
Further, in order to generate stable voltage and current levels during parametric tests, the PMU""s 120 typically include discrete analog circuitry (not shown) for providing feedback control of the voltage and current levels.
In a typical test configuration, only the driver/receiver channel 118 or the PMU 120 in a pin slice circuit 114 is active at one time. Accordingly, switches or relays (not shown) are normally used to keep the driver/receiver channels 118 and the PMU""s 120 isolated from each other.
We have recognized that a significant part of the size and cost of a pin slice circuit is due to the discrete analog circuitry used in the circuit. Because a tester may include thousands of pin slice circuits, reducing the amount of discrete analog circuitry used could substantially affect the size and cost of the tester.
We have further recognized that another significant part of the size and cost of a pin slice circuit is attributable to the size of IC""s used in the circuit.
It would therefore be desirable to have a tester with reduced size and cost that can successfully test electronic devices or assemblies. It would also be desirable to achieve reduced size and cost in a tester designed using pin slice architecture.
With the foregoing background in mind, it is an object of the invention to reduce both the size and cost of a tester.
Another object of the invention is to increase the amount of pin slice circuitry that is implemented using low-cost CMOS technology.
Still another object of the invention is to reduce the size of IC""s used in the pin slice circuitry.
The foregoing and other objects are achieved by providing a tester with multiple pin slice circuits, each pin slice circuit including circuitry implemented using CMOS technology and circuitry implemented using bipolar technology. In a preferred embodiment, the CMOS circuitry includes multiple digital sigma delta modulators, each digital sigma delta modulator producing a bit stream representative of a sequence of analog reference voltage levels; and, the bipolar circuitry includes multiple digital sigma delta decoders, each digital sigma delta decoder receiving a bit stream from a respective digital sigma delta modulator and converting the bit stream into a sequence of analog reference voltage levels. Each sequence of analog reference voltage levels is then provided to circuitry such as a driver/receiver channel and/or a parametric measurement unit.
According to one feature, the digital sigma delta modulator circuitry includes circuitry for combining the multiple bit streams onto a limited number of lines. According to another feature of the invention, the digital sigma delta decoder circuitry includes circuitry for segregating the multiple bit streams from the limited number of lines.
In another embodiment, a serial bit stream is provided to an integrated circuit chip. Next, circuitry on the integrated circuit chip is used to segregate the serial bit stream into a plurality of segregated bit streams. The segregated bit streams are then used to generate analog reference levels for driver/receiver circuitry in the integrated circuit chip.
According to one feature, the integrated circuit chip is implemented using bipolar technology.
In still another embodiment, a semiconductor wafer is provided with a plurality of dies. Next, the dies are tested using driver/receiver circuitry implemented in an integrated circuit chip, thereby identifying good dies. The good dies are then packaged.
According to one feature, the driver/receiver circuitry is provided with reference levels produced from digital bit streams.
In yet another embodiment, the bipolar circuitry includes a parametric measurement unit, which generates and measures DC voltage and current levels; and, the CMOS circuitry includes a digital signal processing device, which monitors and controls the generation of the DC voltage and current levels.
According to one feature, the parametric measurement unit includes a low current section and a high current section, both of which are selectively monitored and controlled by the digital signal processing device.
According to another feature, reference levels used by the parametric measurement unit are provided by digital sigma delta modulators and digital sigma delta decoders.
In another embodiment, the reference levels used by the parametric measurement unit are provided by D-to-A converters controlled by the digital signal processing device.
According to still another feature, the digital signal processing device controls the low current section and the high current section of the parametric measurement unit by controlling inputs to the digital sigma delta modulators.
According to yet another feature, the digital signal processing device controls the low current section and the high current section of the parametric measurement unit by controlling inputs to drivers included in the parametric measurement unit.
Still further objects and advantages will become apparent from a consideration of the ensuing description and drawings.